Archie3d/stochastic_fpga_synth

Stochastic computing audio synthesizer

Applying Stochastic Computing to Audio Synthesis

This project is an attempt to use stochastic computing to build an audio synthesizer on FPGA.

All the experiments has been performed on Altera Cyclone IV FPGA (EP4CE15F23C8) with master clock at 100MHz (via PLL). HDL code is compiled with Quartus Prime 20.1.0.

• Stochastic computing
• Synthesizer architecture
• Dealing with the noise

Sound example

• 🔈 3 oscilators raw
• 🔈 6 oscillators with modulated filter