Arlet/verilog-6502

Issues

• License?

  #6 opened 3 months ago by anders-code
  1

• ALU is a name conflict with GOWIN FPGAs

  #5 opened 5 months ago by stacksmith
  0

• Write (WE) active during reset

  #4 opened a year ago by jesari-git
  1

• Verilator build warnings

  #2 opened 10 years ago by kallisti5
  1

• Store instruction seems to write to wrong address

  #3 opened 9 years ago
  9

• Doesn't build in verilator

  #1 opened 10 years ago by kallisti5
  3