Work In Progress
I intend to create a simple UART Baudrate converter using a FIFO, and synthesize it on an FPGA. The aim is to convert bursts of data from a high baudrate into lower baudrates, or to convert lower baudrates into higher baudrates with an added latency.
Note: fifo.v has been taken from https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/; it is not my code.