Artityagi123456789
B.tech with Electronic and Communication. commitment 👍 ✅100DaysofRTL ➡100Days Verification ➡15Daysof UVM
India
Pinned Repositories
-100dasofSystemVerilog
System Verilog using Functional Verification
100DaysofRTL
100daysofVerification
Day:1 to 5 => Cache Mapping
15DaysofUVM
AMBA_AXI_AHB_APB_notes
AMBA bus lecture material
Artityagi123456789
Config files for my GitHub profile.
Memory_Design_Project
Project
1. Synchronous FIFO
SysSystemVerilog_Practice_Code
System Verilog For Functional Verification
System_Verilog-Constraint_Solution
Artityagi123456789's Repositories
Artityagi123456789/100DaysofRTL
Artityagi123456789/15DaysofUVM
Artityagi123456789/-100dasofSystemVerilog
System Verilog using Functional Verification
Artityagi123456789/Project
1. Synchronous FIFO
Artityagi123456789/SysSystemVerilog_Practice_Code
System Verilog For Functional Verification
Artityagi123456789/System_Verilog-Constraint_Solution
Artityagi123456789/100daysofVerification
Day:1 to 5 => Cache Mapping
Artityagi123456789/200-Programming-in-Verification
Artityagi123456789/Memory_Design_Project
Artityagi123456789/Synchronous_FIFO_Project
Artityagi123456789/SystemVerilog_Book
Books
Artityagi123456789/Verilog_Course_Report
Digital Design using Verilog
Artityagi123456789/Verilog_handwritten_notes
hardware Modeling Using Verilog #(Prof. INDRANIL Sengupta -IIT KHARAGPUR)
Artityagi123456789/Verilog_Practice_Code
Digital Design using Verilog
Artityagi123456789/System_Verilog_project
Ethernet Frame Fields
Artityagi123456789/100-days-of-RTL
probable journey of RTL coding ft. Chandra Prakash
Artityagi123456789/APB_PROTOCOL
verilog
Artityagi123456789/Asynchronous_FIFO_Project
Artityagi123456789/C_Language
C_Program
Artityagi123456789/FIFO_SVA_PROJECT
Artityagi123456789/Hackerrank-Problem-Solving-Python-Solutions
Hackerrank Problem solving solutions in Python
Artityagi123456789/Internship_IERY
Artityagi123456789/python-in-uvm
The UVM written in Python
Artityagi123456789/Router-1x3
Artityagi123456789/SureTrust_Verilog_Course_report
Artityagi123456789/SystemVerilog
Artityagi123456789/systemverilog-homework
SystemVerilog language-oriented exercises
Artityagi123456789/SystemVerilog_30DAYS
30 days of System Verilog to finish complete System verilog
Artityagi123456789/UVM-30DAYS
30 days of UVM to cover all-most all concept of UVM
Artityagi123456789/VLSI_Frontend_Pdf_Notes