/Cordic_accelerator

Accelerator IP for computing transcendental functions using CORDIC algorithm

Primary LanguageSystemVerilogGNU General Public License v3.0GPL-3.0

Cordic_accelerator

Accelerator IP for computing transcendental functions using CORDIC algorithm.

As part of final year project for APJ Abdul Kalam Technological University B Tech Electronics and Communication Program.

Poster page 1

Poster page 2

Department of Electronics and Communication Engineering

Government Engineering College Thrissur


Index

  • docs : Documentation
  • incl : .svh files included in RTL or TB code
  • rtl : Synthesizable components written in system verilog
  • tb : Testbenches written in system verilog
  • test : Test code to be run on the processor
  • utils : Python scripts for generating lookup tables, helper functions for jupyter notebook, etc

Coding guidelines

For synthesizable verilog code and testbench code thats not inside classes, use the following conventions

Prefix Meaning
i_ Input port
o_ Output port
p_ Parameter (or localparam)
r_ Register
w_ Wire
s_ State definitions (as localparam)
e_ Event
Type Case
Variable name camelCase
Function name camelCase
Type name PascalCase
`define macro UPPERCASE
Parameters UPPERCASE

Indentation must be done using spaces, with 2 spaces for each level


Contributors