This repository contains the Verilog code for my MIPS32 processor on FPGA. I wrote it for the Computer Architecture course ECE 369 at the University of arizona. It is the base for the multi-core processor I designed for the ECE 369 processor-on-FPGA competition and is able to run my implementation of the SAD algorithm in assembly. This implementation showcases a pipelined architecture for a subset of the MIPS32 instruction set. It can be used as a basis for a full MIPS32 processor implementation by adding missing features like a Floating Point Unit (FPU), cache levels, and exception handling.
This processor block was written for the Digilent Nexys 4 board containing the Xilinx Artix-7 FPGA, but it can be easily adapted to any other board and FPGA by modifying the contraint file Two4DigitDisplay.xdc. At the FPGA level, the block's inputs are the board oscillator pin as a clock and a push-button pin as a user reset button. The block's outputs are the pins for the 8-digit 7-segment display.
The main content is the Verilog source files in which the processor hardware description code is written. The repository also contains the simulation testbench and the contraint file for the FPGA board. Three test programs are included with their assembly codes, instruction memories, data memories, and expected outputs.
The Verilog code was sucessfully sythesized and tested with the Artix-7 FPGA using the Xilinx Vivado IDE. I would recommend creating a new project with the XC7A100T-1CSG324C FPGA target and copying the files into its source directory. The top level file should be set as the top level block before running simulations or synthesis.
The top level file connects the high-level modules. The processor's output, which is the last written register value, is passed to the 8-digit 7-segment display driver block which uses the 7-segment display driver block. The processor is driven by the board oscillator input passed through a clock divider. The divider ensures the processor is slow enough for the user to see the written register values change on the display.
The processor pipeline is split into five stages as shown in the schematic above. Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), and Write Back (WB). The stages are separated by pipeline registers that buffer the output of each stage for the next clock cycle. The IF unit handles the program counter and reads from the instruction memory. The ID unit decode the instruction into the right register values from its register file and control signals using the control unit and compare unit. The Ex unit makes requested ahrithmetic operations using the Ahrithmetic and Logic Unit (ALU) and selects which values and control signals need to be passed further. The MEM unit reads from and writes to its data memory. The WB unit writes back values to the register file used by the ID unit.
The processor is designed to run a single application starting at address 0. The instruction and data memories are separate in the pipeline. Each of them is preloaded using its memory file (instruction_memory.mem and data_memory.mem). Both the instruction and data memories are assembled from the program's assembly file (instruction.s). The output shown on the simulation testbench waveform or the FPGA board's 8-digital 7-segment display is the new value of the register written in the last clock cycle. Expected outputs are shown in output.txt files.