Pinned Repositories
Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop
Badboy1307
Config files for my GitHub profile.
CAD-Algorithms
This is the repo for submitting your CAD Algorithms
caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel_carrier
Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
educational-materials
Educational materials for RISC-V
improved-goggles
OpenLane__Documentation
OpenLane Documentation
OpenSourceTCAD
Easy access to OpenSource TCAD Tools
Sky130_RTL_Synth_Workshop
Badboy1307's Repositories
Badboy1307/Advanced_Physical_Design_using_OpenLANE_Sky130_Workshop
Badboy1307/Badboy1307
Config files for my GitHub profile.
Badboy1307/CAD-Algorithms
This is the repo for submitting your CAD Algorithms
Badboy1307/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Badboy1307/caravel_carrier
Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
Badboy1307/DFFRAM
Standard Cell Library based Memory Compiler using DFF cells
Badboy1307/dpll
A collection of phase locked loop (PLL) related projects
Badboy1307/edalize
An abstraction library for interfacing EDA tools
Badboy1307/hummingbird
Hummingbird compiles trained ML models into tensor computation for faster inference.
Badboy1307/mflowgen
mflowgen -- A Modular ASIC/FPGA Flow Generator
Badboy1307/ML-For-Beginners
12 weeks, 24 lessons, classic Machine Learning for all
Badboy1307/OpenSTA
OpenSTA engine
Badboy1307/react-native-windows
A framework for building native Windows apps with React.
Badboy1307/sky130RTLDesignAndSynthesisWorkshop
Badboy1307/sv2v
SystemVerilog to Verilog conversion
Badboy1307/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Badboy1307/Windows-Machine-Learning
Samples and Tools for Windows ML.
Badboy1307/improved-goggles
Badboy1307/OpenLane__Documentation
OpenLane Documentation
Badboy1307/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
Badboy1307/Awesome-Sky130-IPs
Badboy1307/f4pga
FOSS Flow For FPGA
Badboy1307/github-slideshow
A robot powered training repository :robot:
Badboy1307/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Badboy1307/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Badboy1307/mcy
Mutation Cover with Yosys (MCY)
Badboy1307/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
Badboy1307/sby
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
Badboy1307/sky130_workspace
Install xschem + xschem_sky130 + skywater-pdk + ngspice +adms +ASITICsky130
Badboy1307/Vehicle-Warning-Indicator-System
A deep learning and computer vision based warning indicator system for the vehicle drivers using live dash-cam footage.