BalaDhinesh

Accelerating-Mandelbrot-Fractal-on-FPGA

Hardware acceleration of mandelbrot fractal generation on PYNQ-Z1 FPGA as part of EE5332 IIT Madras course project

Accelerating_Standard_and_Modified_AES128

Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms

al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

Bitonic-Sorting-In-Verilog

Bitonic Sorting in Verilog which sorts any number of elements which are a power of two

circuit-solver.github.io

This is Circuit Solver which can solve any kind of circuit for you. Do check it out!!

Digital-Design-on-FPGA--Phaseshift22

This course will be an in-depth hands-on demo session on the Virtual FPGA Lab using the open-source Makerchip IDE Web platform.

GettingStartedWithFPGAs

Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.

riscv-bitmanip

RISC-V Bit Manipulation extension, CAD for VLSI(CS6230) Course project, IIT Madras

WikipediaCrawler

Virtual-FPGA-Lab

This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.

BalaDhinesh/Accelerating_Standard_and_Modified_AES128

Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms

BalaDhinesh/Accelerating-Mandelbrot-Fractal-on-FPGA

Hardware acceleration of mandelbrot fractal generation on PYNQ-Z1 FPGA as part of EE5332 IIT Madras course project

BalaDhinesh/Digital-Design-on-FPGA--Phaseshift22

This course will be an in-depth hands-on demo session on the Virtual FPGA Lab using the open-source Makerchip IDE Web platform.

BalaDhinesh/Bitonic-Sorting-In-Verilog

Bitonic Sorting in Verilog which sorts any number of elements which are a power of two

BalaDhinesh/GettingStartedWithFPGAs

Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.

BalaDhinesh/riscv-bitmanip

RISC-V Bit Manipulation extension, CAD for VLSI(CS6230) Course project, IIT Madras

BalaDhinesh/al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

BalaDhinesh/baladhinesh.github.io

Personal website

BalaDhinesh/circuit-solver.github.io

This is Circuit Solver which can solve any kind of circuit for you. Do check it out!!

BalaDhinesh/WikipediaCrawler

BalaDhinesh/Camera-stack-in-smartphones

BalaDhinesh/ComputerArchitecture-CS6600

BalaDhinesh/CoronavirusHeatmap

BalaDhinesh/EE06_Projtask1

Project draft on how to implement keyboard and touchpad on a single hardware and toggling between them

BalaDhinesh/elec-club_cord_self-project

BalaDhinesh/elec_coord_self_project

Electronics Club Self Project for Coordinators

BalaDhinesh/Electronics-Club-MS-Website

This is a website for Mega Session 2022 conducted by Electronics Club, CFI.

BalaDhinesh/ElectronicsClub-MiniTask3

BalaDhinesh/ElectronicsClub-MiniTask4

BalaDhinesh/FPGA-Remote-Lab-Setup

This project FPGA Remote Lab Setup is part of mini-project guided by Prof. Nitin Chandarchoodan, EE IITM

BalaDhinesh/GradePrediction-MLproject

BalaDhinesh/IITM_Sports_website

BalaDhinesh/makerchip_examples

BalaDhinesh/MNA-Circuit-Solver

BalaDhinesh/risc-v-myth-workshop-august-mukuljava

risc-v-myth-workshop-august-mukuljava created by GitHub Classroom

BalaDhinesh/RISC-V_MYTH_Workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

BalaDhinesh/RISCV_MYTH_WORKSHOP

BalaDhinesh/Shaastra-FPGA-Workshop

BalaDhinesh/ultra-maple-42121

Personal portfolio website. Repo is WORK IN PROGRESS

BalaDhinesh/Web-Development

Some basic projects