Verilog Workplace

Test by IVerilog

Move file COMPONENT_tb.v to this directory;
Run:
```
make aCOMPONENT_tb
```
Run:
```
make wCOMPONENT_tb
```

Build on the board

Not recommended.

Move Top.v and UCF file out to the same directory as this readme
copy all files and directories at the same directory as this readme to the project folder
Load to the board

License

EVERYTHING UNDER THE SAME DIRECTORY IS OWNED BY 3170106317 AND IS PRIVATE, AND SHALL NOT BE RE-DISTRIBUTED.

Tutorial

https://www.fpga4student.com/
blocking vs non-blocking - https://youtu.be/kwgvU2MIq1I

Notes

Remove Latches

Make sure all cases are implemented with default cases, all if statements with else statements.

Outdated read problem

always @(state) began
    case (state)
        state1: began
            shiftRegister = 1;
        end
        state2: began
            // read register
        end
    endcase
end

... When reading the register, the value has not been shifted.

To solve the problem (to get the updated value):

always @(*) began
    case (state)
        state1: began
            shiftRegister = 1;
        end
        state2: began
            // read register
        end
    endcase
end

Banyc/Verilog-Workplace