Our goal in this project to design a fast Binary multiplier , using different concepts and approaches for designing the parts that will be used in implementation , the multiplier will be constructed structurally in VHDL , and it will consist like any logic circuit from basic logic gates (inverter , AND , OR , NAND , NOR , XOR and XNOR ) , and those gate will be used to implement two types of Adders: Ripple Carry Adder and Carry look ahead Adder .
in The Second Part of the Project will handle the Verification for the design using exhaustive testing technique, which include testing all possible values for input and monitor the output of the multiplier , and to do that we built a Test Generator that will generate all Possible Test Vector Continuously , on the other hand due to the large number of Test Vectors we designed An analyzer Circuit which will decide if the output of the Multiplier is Correct or not by comparing Result with Actual Result that we got using original Multiplication ( * ) operation .