BigEd/verilog-6502

Issues

• status register P is not variable-width as it should be

  #10 opened 12 years ago by BigEd
  0

• single base register for task relocation

  #9 opened 13 years ago by BigEd
  0

• support single-byte pointers (addresses)

  #8 opened 13 years ago by BigEd
  0

• add long distance shifting

  #7 opened 13 years ago by BigEd
  0

• add an unsigned multiply instruction

  #6 opened 13 years ago by BigEd
  0

• add XBA to provide a B register

  #5 opened 13 years ago by BigEd
  0

• Add stack-relative operations

  #4 opened 13 years ago by BigEd
  0

• Add PHX/PLX and PHY/PLY

  #3 opened 13 years ago by BigEd
  1

• Add BSR

  #2 opened 13 years ago by BigEd
  0

• Add BRA

  #1 opened 13 years ago by BigEd
  0