Bkisa

Bkisa's Stars

• aiminickwong/H264

  H264视频解码verilog实现

  Language:Verilog7938

• tconlon03/FPGA-Object-detection

  Vivado HLS code for object detection using MOG, opening and closing operations and BLOB detection

  Language:C++62

• oguzkaran/Java-Libraries-Development

  Language:Java6

• ehabqadah/spring-boot-microservices-best-practices

  Best Practices for Developing Rest-Based Microservices with Spring-Boot

  Language:Java9130

• codecrafters-io/build-your-own-x

  Master programming by recreating your favorite technologies from scratch.

  Language:Markdown325k30.1k

• cozis/microtcp

  A minimal TCP/IP stack

  Language:C51413

• paritytech/polkadot-sdk

  The Parity Polkadot Blockchain SDK

  Language:Rust2k768

• rwf2/Rocket

  A web framework for Rust.

  Language:Rust24.8k1.6k

• oguzkaran/Java-Aug-2023

  Java-Aug-2023

  Language:Java1716

• changwoolee/lenet5_hls

  FPGA Accelerator for CNN using Vivado HLS

  Language:C++30892

• dhm2013724/yolov2_xilinx_fpga

  A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

  Language:C805236

• mryab/efficient-dl-systems

  Efficient Deep Learning Systems course materials (HSE, YSDA)

  Language:Jupyter Notebook717114

• Deci-AI/super-gradients

  Easily train or fine-tune SOTA computer vision models with one open source training library. The home of Yolo-NAS.

  Language:Jupyter Notebook4.6k518

• suisuisi/Accelerating-CNN-with-FPGA

  This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

  176

• KASIRGA-KIZIL/tekno-kizil

  KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

  Language:Verilog14611

• zahraEbrahimiCFAED/JPEG-Encoder-Image-Compression

  JPEG Encoder for HLS

  Language:C++9

• slaclab/surf

  A huge VHDL library for FPGA development

  Language:VHDL35961

• google/xls

  XLS: Accelerated HW Synthesis

  Language:C++1.2k182

• vortexgpgpu/vortex

  Language:Verilog1.3k281

• f-rivo/systolic-fir

  Design and implementation of a FIR filter with Vivado HLS. The filter uses a systolic C++ description for efficient FPGA implementation.

  Language:C++2

• sld-columbia/esp

  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

  Language:C351109

• spcl/hls_tutorial_examples

  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

  Language:C++19846

• elanmart/cbp-translate

  Language:Python1.3k53

• spcl/gemm_hls

  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

  Language:C++31655

• abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

  IC implementation of Systolic Array for TPU

  Language:Verilog17026

• mcabinaya/Digital-Image-Processing

  My works for EE 569 - Digital Image Processing - Spring 2018 - Graduate Coursework at USC - Dr. C.-C. Jay Kuo

  Language:C++5218

• KastnerRG/pp4fpgas

  Parallel Programming for FPGAs -- An open-source high-level synthesis book

  Language:TeX807149

• hamsternz/Full_Stack_GPS_Receiver

  A Software GPS decoder, going from raw 1-bit ADC samples to position fix

  Language:C15932

• PacoReinaCampo/MPSoC-NTM

  Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV

  Language:SystemVerilog122

• hVHDL/hVHDL_example_project

  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs

  Language:VHDL263