feat: speed up Vivado HLS
Blaok opened this issue · 4 comments
Blaok commented
Current dataflow optimization makes every single invocation of the same module function go through high-level synthesis sequentially, which makes the design flow even less scalable. It is possible to use a RTL flow to get it over with.
Blaok commented
We need this for an efficient haoda backend.
Blaok commented
Leave this for the optimization phase.
Blaok commented
After a few experiments, I think this is very doable via the following steps:
- Generate a
kernel.xml - Generate the Verilog modules
- Generate the top level module
- Pack the modules into a
.xo