Issues
- 1
How to run on FPGA
#54 opened by jiaoyuming1 - 0
- 1
feat: support max, min, select, etc.
#10 opened by Blaok - 1
feat: support Intel flow
#41 opened by Blaok - 2
feat: avoid iteration counter
#24 opened by Blaok - 4
feat: speed up Vivado HLS
#38 opened by Blaok - 3
feat: support multiple inputs and outputs
#21 opened by Blaok - 0
- 0
feat: support separated packing/unpacking modules
#42 opened by Blaok - 1
feat: support assignment in expression
#22 opened by Blaok - 2
fix: support multiple DRAM banks properly
#39 opened by Blaok - 0
feat: vectorization-based module merging
#30 opened by Blaok - 2
fix: support multiple channels
#3 opened by Blaok - 2
feat: avoid dependence on CPython 3.6
#31 opened by Blaok - 5
refactor: code clean up and coding style convention
#29 opened by Blaok - 0
test: add unittest
#34 opened by Blaok - 1
refactor: rename to soda
#28 opened by Blaok - 1
- 1
fix: offset analysis is incorrect in some cases
#20 opened by Blaok - 2
feat: disable aux parameters when possible
#4 opened by Blaok - 1
feat: padding borders
#16 opened by Blaok - 4
feat: support iteration generation
#12 opened by Blaok - 2
feat: semantic check
#9 opened by Blaok - 1
fix: routing problems
#14 opened by Blaok - 1
feat: support multiple stages/iterations
#2 opened by Blaok - 1
fix: support extra parameters
#6 opened by Blaok - 0
feat: compile from a DSL
#5 opened by Blaok