Blxoe

Blxoe's Stars

• riscv-boom/riscv-boom

  SonicBOOM: The Berkeley Out-of-Order Machine

  Language:Scala1.7k421

• pulkit5678/Asynchronous-FIFO

  References: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

  Language:Verilog1

• kaxap/arl

  lists of most popular repositories for most favoured programming languages (according to StackOverflow)

  Language:Python1.9k185

• ultraembedded/core_ddr3_controller

  A DDR3 memory controller in Verilog for various FPGAs

  Language:Verilog35384

• rogerlarsson/awesome-opensource-hardware

  List of awesome open source hardware tools, generators, and reusable designs

  1

• OpenTimer/OpenTimer

  A High-performance Timing Analysis Tool for VLSI Systems

  Language:Verilog555143

• PrincetonUniversity/openpiton

  The OpenPiton Platform

  Language:Assembly630212

• open-sdr/openwifi-hw

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

  Language:Verilog680233

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python724224

• circuitvalley/USB_C_Industrial_Camera_FPGA_USB3

  Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

  Language:Verilog817149

• FPGAwars/apio

  :seedling: Open source ecosystem for open FPGA boards

  Language:Verilog797136

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog848274

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog853146

• mntmn/amiga2000-gfxcard

  MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

  Language:Verilog99777

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k290

• google/xls

  XLS: Accelerated HW Synthesis

  Language:C++1.2k177

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k230

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k438

• jbush001/NyuziProcessor

  GPGPU microprocessor architecture

  Language:C2k352

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k282

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k694

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.5k414

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.2k340

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.8k525

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  3.9k658

• open-sdr/openwifi

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  Language:C3.8k649

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala3.9k594

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7k523

• hehonghui/awesome-english-ebooks

  经济学人(含音频)、纽约客、卫报、连线、大西洋月刊等英语杂志免费下载,支持epub、mobi、pdf格式, 每周更新

  Language:CSS21.4k1.7k