This the project of Computer Architecture 2016 Fall, NTU.
- Tag Project 1: Pipelined MIPS CPU in Verilog
- Tag Project 2: L1 Cache
For more details, please refer to report
directory.
- and, or
- add, sub, mul,
- addi
- lw, sw
- beq, j
Handle data hazard and control hazard with stalls or forwarding
L1 data cache
Type | Value | Version |
---|---|---|
Compiler | Icarus Verilog | 10.1 (stable) (v10_1) |
Runtime Engine | Icarus Verilog Runtime | 10.1 (stable) (v10_1) |