Pinned Repositories
32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
accelerator
The design of an accelerator for DRAM based on E203.
async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
Flash_controller
基于spi协议的flash控制器设计，flash为64Mb位串行NOR闪存MX25L6436F
hbird-e-sdk
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
nanoDAP-wireless
nanoDAP-wireless无线仿真器用户手册
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
risc_cpu
CJH8668's Repositories
CJH8668/risc_cpu
CJH8668/32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
CJH8668/accelerator
The design of an accelerator for DRAM based on E203.
CJH8668/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
CJH8668/Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
CJH8668/Flash_controller
基于spi协议的flash控制器设计，flash为64Mb位串行NOR闪存MX25L6436F
CJH8668/hbird-e-sdk
Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
CJH8668/hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
CJH8668/nanoDAP-wireless
nanoDAP-wireless无线仿真器用户手册
CJH8668/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
CJH8668/prim-benchmarks
PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (preliminary version at https://arxiv.org/abs/2105.03814).
CJH8668/ResearchNote
通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)
CJH8668/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
CJH8668/verilog-axi
Verilog AXI components for FPGA implementation