Pinned Repositories
.github
carp_pcb
CARPOpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
cocotbext-wishbone
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
ramp-core
RAMP's out of order RV32G processor, implemented with PyMTL3
riscv32-csr
sram22-hammer
A configurable SRAM generator
style-guide
The SystemVerilog style guide for the RAMP framework.
tapeout-ci-2311
caravel-user repository for November 6, 2023 tapeout
Cal Poly CARP's Repositories
Cal-Poly-RAMP/ramp-core
RAMP's out of order RV32G processor, implemented with PyMTL3
Cal-Poly-RAMP/CARPOpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Cal-Poly-RAMP/tapeout-ci-2311
caravel-user repository for November 6, 2023 tapeout
Cal-Poly-RAMP/.github
Cal-Poly-RAMP/basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
Cal-Poly-RAMP/cal-poly-ramp.github.io
Website for the RAMP framework
Cal-Poly-RAMP/carp_pcb
Cal-Poly-RAMP/cocotbext-wishbone
Cal-Poly-RAMP/qspiflash
A set of Wishbone Controlled SPI Flash Controllers
Cal-Poly-RAMP/riscv32-csr
Cal-Poly-RAMP/sky130_sram_macros
Cal-Poly-RAMP/sram22-hammer
A configurable SRAM generator
Cal-Poly-RAMP/style-guide
The SystemVerilog style guide for the RAMP framework.