These are excercises and experiments for the Terasic DE0-Nano development board, which has a Cyclone IV FPGA from Intel (Altera). The IDE is Quartus Prime Lite.
Mostly using Verilog. Maybe some VHDL.
CarlRaymond/DE0-Nano
Experiments with Terasic DE0-Nano development board for Altera / Intel Cyclone IV FPGA
Verilog