/STL

IC digital design common used module

Primary LanguageSystemVerilog

Standard lib

This library contain all of the commonly used HW primitives. Some of them are from github and some write by myself. Use these primitives to build your modules will save lot's of design and verfiy time. Both the power and area can under control by using these primitives to build your module.

Content

  • LowRISC: is the ips from opentitan, prim and prim_genric is the basic primitives. These primivtives include: fifo, arbiter, crc, ecc, useful Macro etc.

  • Common: is the ip write by myself include: sort, compare tree, pipe-line control, swtichs, interface, useful Macro etc.

  • NOC is a lite weight 2D mesh network, use X-Y routing algorithm to avoid deadlock.

Basic Coding Guide

This repository contains style guides curated by lowRISC for use in our code and documentation.