ChenWendi2001/MIPS-CPU
A 5-stage pipelined MIPS processor 💻, which supports stall, forwarding, branch-not-taken and cache.
Verilog
No issues in this repository yet.
A 5-stage pipelined MIPS processor 💻, which supports stall, forwarding, branch-not-taken and cache.
Verilog
No issues in this repository yet.