ChingSsuyuan/Vivado_State_Machine_Project

Vivado state machine verilog codes

Vivado State Machine Project:

All codes have been tested and simulated at Vivado, all functions operates well when implemented into FPGA board.

The Project includes three parts:

Part1: Store Switch Inputs

Input is a 10-bit binary number, provided via ten switches (each representing one bit). We Store this 10-bit number in a 10-bit shift register. The register will only update its storage after pressing reset button.

Part2: Clock Divider

Change clock cycle from 100MHZ to 1Hz, slow down the clock to implement seven segements display in 1 Instruction/Second

Part3: State Machine

101 Sequence Detector with Overlap