All codes have been tested and simulated at Vivado, all functions operates well when implemented into FPGA board.
Input is a 10-bit binary number, provided via ten switches (each representing one bit). We Store this 10-bit number in a 10-bit shift register. The register will only update its storage after pressing reset button.
Change clock cycle from 100MHZ to 1Hz, slow down the clock to implement seven segements display in 1 Instruction/Second
101 Sequence Detector with Overlap