ChipFlow

Pinned Repositories

amaranth-orchard
Language:Python2 2 01
caravel_user_project_mpw3
https://caravel-user-project.readthedocs.io
Language:Verilog3 0 00
caravel_user_project_mpw5
Submission repo for MPW5
Language:Coq0 1 10
chipflow-tools
Multi-platform nightly builds of open source digital design and verification tools
Language:Python1 0 00
chipflow.github.io
ChipFlow GitHub pages
Language:HTML00
docs
ChipFlow docs.
0 1 00
example-socs
Language:Python4 3 02
ieee754fpu
Language:Python2 3 00
IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Language:HTML0 0 00
mpw4
SoC and build scripts for MPW4
Language:Python5 4 11

ChipFlow's Repositories

ChipFlow/mpw4
SoC and build scripts for MPW4
Language:Python5 4 11
ChipFlow/example-socs
Language:Python4 3 02
ChipFlow/caravel_user_project_mpw3
https://caravel-user-project.readthedocs.io
Language:Verilog3 0 00
ChipFlow/amaranth-orchard
Language:Python2 2 01
ChipFlow/ieee754fpu
Language:Python2 3 00
ChipFlow/chipflow-tools
Multi-platform nightly builds of open source digital design and verification tools
Language:Python1 0 00
ChipFlow/amaranth-vexriscv
Language:Verilog00
ChipFlow/caravel_user_project_mpw5
Submission repo for MPW5
Language:Coq0 1 10
ChipFlow/chipflow.github.io
ChipFlow GitHub pages
Language:HTML00
ChipFlow/docs
ChipFlow docs.
0 1 00
ChipFlow/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Language:HTML0 0 00
ChipFlow/lefdefrw
Reader/Writer for DEF&LEF files with separate parse schema and read/write state machines
0 2 00
ChipFlow/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language:Verilog0 0 00
ChipFlow/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog0 0 00
ChipFlow/amaranth
A modern hardware definition language and toolchain based on Python
Language:Python0 0
ChipFlow/amaranth-cv32e40p
CV32E40P Integration for Amaranth
Language:Verilog3 0
ChipFlow/amaranth-soc
System on Chip toolkit for Amaranth HDL
Language:Python0 0
ChipFlow/caravel_user_project_mpw4
Submission repo with GDS for MPW4
Language:Verilog1 0
ChipFlow/chipflow-docs
ChipFlow/chipflow-lib
Language:Python2 01
ChipFlow/coriolis
Coriolis VLSI EDA Tool (LIP6)
Language:C++0 0
ChipFlow/emscripten
Emscripten: An LLVM-to-WebAssembly Compiler
Language:C0 0
ChipFlow/lambdasoc
Language:Python0 0
ChipFlow/lambdasoc-bios
Language:C0 0
ChipFlow/luna
a USB multitool + Amaranth HDL framework for monitoring, hacking, and developing USB devices
ChipFlow/xyce-docker
Build a docker image with Xyce dependencies prebuilt, based on focal
Language:Shell0 0