This project serves as a simple reference design for using the onboard DDR2 memory with Xilinx MIG IP of the Nexys 4 DDR / Nexys A7 FPGA Trainer board.
The included step-by-step PDF guide walks through the configuration process.
ChrisPVille/mig_example
Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
Verilog