CoffeeTonight
ASIC Engineer by Day, Opensource User by Night, Dreamer by Dawn
Principal EngineerSeoul, Korea
Pinned Repositories
CodeFromAI
magma
magma circuits
myhdl
The MyHDL development repository
netlist_parser.py
A Python based netlist parser, including Verilog and SPICE
OpenProjects
ply
Python Lex-Yacc
PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
pyslang
Python bindings for slang, a library for compiling SystemVerilog
pyuvm
The UVM written in Python
verilog_parser
To look neat, Convert verilog into metadata.
CoffeeTonight's Repositories
CoffeeTonight/verilog_parser
To look neat, Convert verilog into metadata.
CoffeeTonight/CodeFromAI
CoffeeTonight/magma
magma circuits
CoffeeTonight/myhdl
The MyHDL development repository
CoffeeTonight/netlist_parser.py
A Python based netlist parser, including Verilog and SPICE
CoffeeTonight/OpenProjects
CoffeeTonight/ply
Python Lex-Yacc
CoffeeTonight/PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
CoffeeTonight/pyslang
Python bindings for slang, a library for compiling SystemVerilog
CoffeeTonight/pyuvm
The UVM written in Python
CoffeeTonight/SpaceStreet
First Rep.
CoffeeTonight/sveditor-ref-designs
Reference designs for use in SVEditor benchmarking
CoffeeTonight/systemrdl-compiler
SystemRDL 2.0 language compiler front-end
CoffeeTonight/util
CoffeeTonight/uvm-python
UVM 1.2 port to Python
CoffeeTonight/tvip-axi
AMBA AXI VIP
CoffeeTonight/veripy
VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, various code generation plugins and configurable code generation. The VeriPy Wiki has more the detailed documentation.
CoffeeTonight/XiangShan
Open-source high-performance RISC-V processor