CoreSemi

Pinned Repositories

bootrom
BootROM for JCore J2 SoCs
Language:C5 1 02
gnss-baseband
Baseband Receiver IP for GPS like DSSS signals
Language:VHDL66 2 018
jcore-cpu
J-Core J2/J32 5 stage pipeline CPU core
Language:VHDL7 1 01
jcore-jx
The J-Core Jx Platform board hardware.
4 1 02
jcore-soc
J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.
Language:VHDL7 1 02

CoreSemi's Repositories

CoreSemi/gnss-baseband
Baseband Receiver IP for GPS like DSSS signals
Language:VHDL66 2 018
CoreSemi/jcore-cpu
J-Core J2/J32 5 stage pipeline CPU core
Language:VHDL7 1 01
CoreSemi/jcore-soc
J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.
Language:VHDL7 1 02
CoreSemi/bootrom
BootROM for JCore J2 SoCs
Language:C5 1 02
CoreSemi/jcore-jx
The J-Core Jx Platform board hardware.
4 1 02