Contains lab 4 and all previous labs to be instantiated within lab4:
- lab1
- lab2
- lab3
- lab4
- ALU_control
- control_unit
- imm_gen.vhd
- datapath.vhd
- datapath_test.vhd
- waveforms
- mif_generators
- DE2_115_pin_assignments.csv
- inst_mem.csv
- operations.docx
- operations.xlsx
- lab4report.docx
- inst_mem.mif
- inst_mem.vhd
- inst_mem.qip
- register8.vhd
- programCounter.vhd
- instruction_fetch.vhd
- logicShift.vhd
- fullader.vhd
- ALU_64.vhd
- addsub.vhd
- risc_v_decoder.vhd
- register_file.vhd
This vhdl file contains the same code as the datapath, but with added buffer signals. These buffer sigals are the sigals surrounding the data_mem, ALU and register_file components in order to test correct implementation (see waveform).
waveforms test each component of the datapath sequentially
scripts to generate inst_mem and data_mem .mif files and their complimentary .csv files. See README within folder for usage and system reqirements.
pin assignments for useage with FPGA
csv file containing all 256 instrucitons in the complimentary .mif file. Columns are full instruction then each decoded unit in the instruction.
List of operation on first 46 instructions and their expected output caculations. Needs to be formatted to properly show binary numbers. Rows are not formatted for read time cycles and delays.
Excel file formatted to show binary. Columns are formatted for real time cycles with each row displaying what will be contained in each signal and register on that specific cycle. All ALU results and register current values are also contained within these columns.
Waveforms and timing for each component within the datapath as well as the full datapath.
(we have three of the same breed of dog and they were the three blind mice for Halloween)
