Partly implementation of the asymetric cryptographic algorithm RSA (codification/decodification phases) on a FPGA.
Implementation done in VHDL (RTL desgin and testbench). The IDE used was Xilinx Vivado for both design and validation, and the FPGA used was Xilinx Pynq-Z1. The results were also validated with a small implementation in Python.
Lecture from master "Electronic Systems Design" in NTNU Trondheim.