CroosJJSE

Pinned Repositories

• AXI_Stream_Parallel_to_Serial_Converter

  parameterized parallel to serial converter which is used in many modern devices.

  Language:SystemVerilog11

• Flower_Exchange_Cpp

  a project done by me for the C++ workshop series by LSEG.

  Language:C++10

• UART-Implementation-Using-FPGA

  This is a group assignment done under the module EN2111 Electronic Circuit Design, Semester 4, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

  Language:SystemVerilog10

• AMD_AI_Robotic_Challenge

  Language:Makefile00

• AXI-DMA

  we’ll use the DMA to transfer data from memory to an IP block and back to the memory.

  Language:VHDL00

• BA-LinkedIn

  Language:Python00

• BA-Professional

  00

• basic-blinking-LED

  basic fpga implantation

  Language:Verilog00

• basic-gates

  according to input it will work as AND OR NOR XNOR gates.

  Language:Verilog00

• basic-switch-and-Led

  basic fpga implantation

  Language:Verilog00

CroosJJSE's Repositories