A hardware architecture for task parallelism.
- Python 3.5 or newer
- bsc
- meson
- ninja
- connectal (for FPGA synthesis)
- GNU make (for FPGA synthesis)
- GNU compiler collection a.k.a. gcc (for FPGA synthesis)
- bsc-contrib (for FPGA synthesis)
- verilator (for FPGA simulation)
Copy DefaultPmConfig.bsv
to bsv/PmConfig.bsv
and change the values as desired.
$ meson builddir && cd builddir
$ meson compile
$ ./mkPuppetmasterTestbench
For the commands below to work, two environment variables need to be set:
CONNECTALDIR
to point to the root of the Connectal installation directoryBLUESPECDIR
to point to thelib
subdirectory in the Bluespec installation directory
$ make build.verilator
$ make run.verilator