Pinned Repositories
AI_projects
I am a full-stack engineer for AI projects, glad to share my experience. pratices make the top engineer.
basic_verilog
Must-have verilog systemverilog modules
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
deep-residual-networks
Deep Residual Learning for Image Recognition
e203_hbirdv2
The Ultra-Low Power RISC-V Core
force-riscv
Instruction Set Generator initially contributed by Futurewei
HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
llvm-rv
Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
openc910
OpenXuantie - OpenC910 Core
Cyoruer's Repositories
Cyoruer/AI_projects
I am a full-stack engineer for AI projects, glad to share my experience. pratices make the top engineer.
Cyoruer/basic_verilog
Must-have verilog systemverilog modules
Cyoruer/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Cyoruer/deep-residual-networks
Deep Residual Learning for Image Recognition
Cyoruer/e203_hbirdv2
The Ultra-Low Power RISC-V Core
Cyoruer/force-riscv
Instruction Set Generator initially contributed by Futurewei
Cyoruer/HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
Cyoruer/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Cyoruer/llvm-rv
Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
Cyoruer/openc910
OpenXuantie - OpenC910 Core
Cyoruer/opentitan
OpenTitan: Open source silicon root of trust
Cyoruer/riscv-dv
Random instruction generator for RISC-V processor verification
Cyoruer/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
Cyoruer/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Cyoruer/riscv-torture
RISC-V Torture Test
Cyoruer/tinyriscv
A very simple and easy to understand RISC-V core.