Pinned Repositories
AVS3-RDOQ
This work presents the RTL design from our paper published in the journal TCSVT: 'Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding.'
AXIS-AXI4-AXIS
This project is designed to delay the output of the video stream in AXI-STREAM format.
Chaotic-Carrier-Wave-System-Based-on-FPGA
The frequency of the goal wave is dictated by the value of the logistic value in this chaotic carrier wave system, which is based on fpga design.
DOUDIU
Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm
The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
Multi-core-Paillier-Acceleration-System
This work presents the RTL design of a multi-core Paillier acceleration system. It supports four types of acceleration: Paillier encryption, Paillier decryption, homomorphic addition, and homomorphic scalar multiplication.
serial_port_router
this's a simple case of different bound rate serial port router
Vehicle-License-Plate-Recognition-on-FPGA
Video-Stitching
This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
DOUDIU's Repositories
DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
DOUDIU/Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm
The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
DOUDIU/AXIS-AXI4-AXIS
This project is designed to delay the output of the video stream in AXI-STREAM format.
DOUDIU/Video-Stitching
This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
DOUDIU/Vehicle-License-Plate-Recognition-on-FPGA
DOUDIU/Multi-core-Paillier-Acceleration-System
This work presents the RTL design of a multi-core Paillier acceleration system. It supports four types of acceleration: Paillier encryption, Paillier decryption, homomorphic addition, and homomorphic scalar multiplication.
DOUDIU/DOUDIU
DOUDIU/AVS3-RDOQ
This work presents the RTL design from our paper published in the journal TCSVT: 'Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding.'
DOUDIU/Chaotic-Carrier-Wave-System-Based-on-FPGA
The frequency of the goal wave is dictated by the value of the logistic value in this chaotic carrier wave system, which is based on fpga design.
DOUDIU/serial_port_router
this's a simple case of different bound rate serial port router