CPU INFOrmation library

cpuinfo is a library to detect essential for performance optimization information about host CPU.

Features

Cross-platform availability:
- Linux, Windows, macOS, Android, and iOS operating systems
- x86, x86-64, ARM, and ARM64 architectures
Modern C/C++ interface
- Thread-safe
- No memory allocation after initialization
- No exceptions thrown
Detection of supported instruction sets, up to AVX512 (x86) and ARMv8.3 extensions
Detection of SoC and core information:
- Processor (SoC) name
- Integrated GPU name (Android/iOS only)
- Vendor, microarchitecture, and ID (MIDR on ARM, CPUID leaf 1 EAX value on x86) for each CPU core
Detection of cache information:
- Cache type (instruction/data/unified), size and line size
- Cache associativity
- Cores and logical processors (hyper-threads) sharing the cache
Detection of topology information (relative between logical processors, cores, and processor packages)
Well-tested production-quality code:
- 60+ mock tests based on data from real devices
- Includes work-arounds for common bugs in hardware and OS kernels
- Supports systems with heterogenous cores, such as big.LITTLE and Max.Med.Min
Permissive open-source license (Simplified BSD)

Examples

Log processor name:

cpuinfo_initialize();
printf("Running on %s CPU\n", cpuinfo_get_package(0)->name);

Detect if target is a 32-bit or 64-bit ARM system:

#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
    /* 32-bit ARM-specific code here */
#endif

Check if the host CPU support ARM NEON

cpuinfo_initialize();
if (cpuinfo_has_arm_neon()) {
    neon_implementation(arguments);
}

Check if the host CPU supports x86 AVX

cpuinfo_initialize();
if (cpuinfo_has_x86_avx()) {
    avx_implementation(arguments);
}

Check if the thread runs on a Cortex-A53 core

cpuinfo_initialize();
switch (cpuinfo_get_current_core()->uarch) {
    case cpuinfo_uarch_cortex_a53:
        cortex_a53_implementation(arguments);
        break;
    default:
        generic_implementation(arguments);
        break;
}

Get the size of level 1 data cache on the fastest core in the processor (e.g. big core in big.LITTLE ARM systems):

cpuinfo_initialize();
const size_t l1_size = cpuinfo_get_processor(0)->cache.l1d->size;

Pin thread to cores sharing L2 cache with the current core (Linux or Android)

cpuinfo_initialize();
cpu_set_t cpu_set;
CPU_ZERO(&cpu_set);
const struct cpuinfo_cache* current_l2 = cpuinfo_get_current_processor()->cache.l2;
for (uint32_t i = 0; i < current_l2->processor_count; i++) {
    CPU_SET(cpuinfo_get_processor(current_l2->processor_start + i)->linux_id, &cpu_set);
}
pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpu_set);

Exposed information

Supported environments:

Methods