Damien-Wu

Damien-Wu's Stars

• learnbyexample/py_regular_expressions

  Learn Python Regular Expressions step by step from beginner to advanced levels

  Language:Python1.8k226

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.6k1.2k

• yaozhaosh/e200_opensource

  The Ultra-Low Power RISC Core

  Language:Verilog153

• cnrv/riscv-soc-book

  关于RISC-V你所需要知道的一切

  54766

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog893150

• missing-semester/missing-semester

  The Missing Semester of Your CS Education 📚

  Language:CSS5k1.2k

• huihut/interview

  📚 C/C++ 技术面试基础知识总结，包括语言、程序库、数据结构、算法、系统、网络、链接装载库等知识及面试经验、招聘、内推等信息。This repository is a summary of the basic knowledge of recruiting job seekers and beginners in the direction of C/C++ technology, including language, program library, data structure, algorithm, system, network, link loading library, interview experience, recruitment, recommendation, etc.

  Language:C++35.1k8k

• TheAlgorithms/C

  Collection of various algorithms in mathematics, machine learning, computer science, physics, etc implemented in C for educational purposes.

  Language:C19.5k4.4k

• ZhongYi-LinuxDriverDev/CS-EmbeddedLinux-Book

  嵌入式，计算机常用电子书籍整理，并且附带下载链接，涵盖：ARM体系与架构，C/C++语言，汇编语言，操作系统，计算机网络，计算组成原理，Linux驱动，Linux内核，单片机开发，程序员认知成长，笔试面试技巧等书籍。长期更新中，欢迎star~

  1.3k268

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.4k709

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  850206

• open-sdr/openwifi

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  Language:C4k665

• 521xueweihan/HelloGitHub

  :octocat: 分享 GitHub 上有趣、入门级的开源项目。Share interesting, entry-level open source projects on GitHub.

  Language:Python96.4k9.7k

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.6k463

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• Efinix-Inc/SaxonEFX_Soc

  Language:Scala52

• SpinalHDL/SaxonSoc

  SoC based on VexRiscv and ICE40 UP5K

  Language:Scala15140