stm32h7.c hardcodes PLL_BASE to 5 MHz causing timing errors
calithameridi opened this issue · 3 comments
Clock configuration on stm32h7 hardcodes a PLL_BASE of 5 MHz due to an implicit assumption that HSE is a 25 MHz crystal oscillator, which works for BTT Octopus Pro and Kraken boards. Unfortunately this breaks timing on boards without 25 MHz (e.g. Corevus-G v0.4 with a 12 MHz on HSE) — for example, all moves execute at 20% greater velocity, and more critically a clock frequency above 2^(32) / (10 s) = 429 MHz causes integer overflow errors.
I find that bodging the value of pll_base to 4 MHz allows me to successfully build an image with 400 MHz clock. Obviously this is not a permanent fix although it may suffice in providing pre-built firmware images to Corevus beta-testers
This would also be good to PR into mainline klipper and fix it for EVERYONE, not just DK
This would also be good to PR into mainline klipper and fix it for EVERYONE, not just DK
yeah but they don't have a convenient way of reporting issues