This verilog Repo is inspired by the 8bitworkshop.com and should be regarded as training material. Thus the source code originated from the book "DESIGNING VIDEO GAME HARDWARE IN VERILOG An 8bitworkshop Book" - by Steven Hugg with few changes or comments for learning purpose.
Another useful source: https://marceluda.github.io/rp_dummy/EEOF2018/Verilog_Cheat_Sheet.pdf
Introduction: https://github.com/JeffDeCola/my-verilog-examples#overview
Later: https://8bitworkshop.com/v3.9.0/?platform=verilog&file=cpu6502.v
Later2: https://x.com/BrunoLevy01/status/1595709056009863170
Cool RISCV Implementation from Berkeley Student:
https://github.com/T-K-233/RISC-V-Single-Cycle-CPU/tree/main/BA20X-Verilog)