DejianLin

BRAM_DDR3_HDMI

在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。

fm-transmitter

FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic and so forth.

Realisation_of_32X8-_ROM_using_Xilinx_SysGen

Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming.Simulink allows users to simulate their ideas, which may then be packaged as a Vivado IP and quickly imported into a Vivado project.

Testing_32bit_ALU_using_Xilinx_SysGen

finn

Dataflow compiler for QNN inference on FPGAs

DejianLin/BRAM_DDR3_HDMI

在FPGA中将图像数据输入到DDR3中，再输送到HDMI接口上进行显示。

DejianLin/fm-transmitter

FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic and so forth.

DejianLin/Realisation_of_32X8-_ROM_using_Xilinx_SysGen

Xilinx System Generator for DSP (SysGen) is a MATLAB Simulink add-on that enables the development of architecture-level FPGA designs using graphical blocks programming.Simulink allows users to simulate their ideas, which may then be packaged as a Vivado IP and quickly imported into a Vivado project.

DejianLin/Testing_32bit_ALU_using_Xilinx_SysGen