Devipriya1921
VLSI Enthusiast | Parasitic Extraction | Physical Verification | Physical Design | Opensource EDA | Poet | Author
Applications Engineer @ Synopsys, BangaloreBangalore, India
Pinned Repositories
AdvancedSynthesisandSTAwithDC
avsddac28nm
CMOS-Wallace-Tree-Multiplier
CocoTb_Design_Verification_AXIS_FIFO
challenges-Devipriya1921 created by GitHub Classroom
Physical-Verification-using-synopsys-40nm
Physical_Design_Using_OpenLANE_Sky130
Traffic-Light-Controller-using-Verilog
Verilog Project
VSDBabySoC_ICC2
vsdriscv
vsdserializer_v1
Devipriya1921's Repositories
Devipriya1921/vsdserializer_v1
Devipriya1921/Traffic-Light-Controller-using-Verilog
Verilog Project
Devipriya1921/VSDBabySoC_ICC2
Devipriya1921/Physical_Design_Using_OpenLANE_Sky130
Devipriya1921/Physical-Verification-using-synopsys-40nm
Devipriya1921/vsdriscv
Devipriya1921/AdvancedSynthesisandSTAwithDC
Devipriya1921/avsddac28nm
Devipriya1921/CMOS-Wallace-Tree-Multiplier
Devipriya1921/CocoTb_Design_Verification_AXIS_FIFO
challenges-Devipriya1921 created by GitHub Classroom
Devipriya1921/VSDBabySoC-Functional_Netlisting
Devipriya1921/CPU_Processor_riscv_myth-Devipriya
riscv_myth_workshop_may22-Devipriya1921 created by GitHub Classroom
Devipriya1921/Devipriya1921
Devipriya1921/Google-skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Devipriya1921/magic-OpenSource-Tool
Magic VLSI Layout Tool
Devipriya1921/Malayalam_NLU_ASR_Samsung_Prism
Devipriya1921/The-OpenROAD-Project-OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Devipriya1921/VSD_Analog_Bandgap_IP_Design_Using_Sky130_PDKs
Devipriya1921/VSD_Digital-Design-using-virtual-FPGA
Devipriya1921/VSD_Open_PLL_OSU180nm
Devipriya1921/vsdflow-OpenSource-EDA-Tools
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes