Digital-EDA/Digital-IDE

Issues

• Outline解析功能崩溃问题定位

  #75 opened 3 months ago by GarenZZ
  0

• Verilog的数字语法高亮

  #74 opened 3 months ago by xqXQzzz1
  0

• 重复仿真时报错

  #45 opened 3 months ago by firerock1
  2

• 报错：verilog解析器无法解析以下代码

  #62 opened 5 months ago by wzw123098
  2

• .v源文件未被正确识别

  #46 opened 3 months ago by bin0612
  2

• 【报错】RuntimeError: null function or function signature mismatch

  #63 opened 5 months ago by mathsmatics
  6

• [0.3.2] 例化模块的类型，模块名称的代码高亮不变色

  #35 opened 9 months ago by DreamLand7707
  2

• 0.3.2 无verilog语法检查，且提示RuntimeError

  #38 opened 3 months ago by LFZhou2000
  3

• 文档中的params和ports数反了

  #34 opened 3 months ago by jxzsxsp
  3

• 【结构树错误 二级bug】点击子模块无法跳转

  #73 opened 3 months ago by Nitcloud
  0

• 基础教程太少

  #47 opened 8 months ago by Liber1917
  3

• 采用iverilog生成的VCD貌似无法解析仿真数据

  #70 opened 4 months ago by chesswei1
  1

• 关于netlist的生成错误

  #43 opened 9 months ago by s-yuan
  1

• 关于波形显示的一些建议

  #71 opened 4 months ago by lancyjk
  0

• 建议：模块例化可以基于文件夹来检索，当文件比较多时更整洁一点。

  #27 opened 4 months ago by MaxWei250
  1

• [0.3.2]param语法错误会弹右下角报错弹窗, TreeView刷新按钮无效

  #29 opened 9 months ago by DuBirdFly
  3

• 插件不能使用

  #44 opened 9 months ago by ZcCarvell
  1

• Errors happen when parsing d:/danpj/fpga/modelsim/mod1/user/src/count4.v. Error: "RuntimeError: null function or function signature mismatch". Just propose a valuable issue in our github repo

  #52 opened 7 months ago by djqingwa
  1

• 报错：RuntimeError: null function or function signature mismatch、无法识别HDL文件

  #55 opened 6 months ago by cyl-0411
  1

• 会尝试读取gowin 的临时文件

  #50 opened 7 months ago by sysytwl
  1

• Maximum call stack size exceeded

  #54 opened 7 months ago by 412192816
  0

• 功能建议-能增加点类似Verilog-Mode的功能么

  #60 opened 5 months ago by qinyalei
  0

• 网表优化与插入文档

  #68 opened 4 months ago by lancyjk
  0

• 【v0.3.2】模块调用后netlist生成错误，且仿真报错

  #69 opened 4 months ago by Autumeqscz
  0

• 插件文档导出问题

  #67 opened 4 months ago by lancyjk
  3

• [0.3.3 beta] 含参数模型的例化存在问题以及拓展快捷键失效的问题

  #66 opened 4 months ago by light-ly
  6

• [0.3.2] [问题] 含参数的 Verilog 模块自动例化，代码格式不正确

  #64 opened 4 months ago by light-ly
  1

• [建议]：优化Formatter与文档生成

  #33 opened 9 months ago by HysenEcho
  2

• 【v0.3.2】testbench修改之后再次仿真会报错

  #65 opened 4 months ago by Autumeqscz
  0

• 报错：verilog解析器的bug

  #61 opened 5 months ago by wzw123098
  1

• 例化模块自动生成tb文件报错Unknown module type

  #53 opened 7 months ago by 412192816
  1

• 自动例化报错

  #51 opened 7 months ago by zjutxzq
  3

• 0.3.0版本后存在bug,构建项目后仿真无法运行

  #28 opened 9 months ago by MaxWei250
  0

• [0.3.2]module的#后的parameter能悬停显示数值, 但内部parameter的不能

  #30 opened 9 months ago by DuBirdFly
  1

• [0.3.2]数值悬停提示不支持'_'语法

  #31 opened 9 months ago by DuBirdFly
  1

• [0.3.2] 模块定义跳转偶尔会出现问题

  #37 opened 9 months ago by DreamLand7707
  1

• 在声明数据位宽时使用宏定义会报错

  #39 opened 9 months ago by Nephino
  0

• [0.3.2] 离线支持+SV支持

  #41 opened 9 months ago by JackBlake
  1

• [0.3.2] 支持对verilator 的dpi-c机制的支持

  #42 opened 9 months ago by CzealChen
  0

• 【0.3.2】【问题】1无法解析localparam 2 带参数模块例化

  #48 opened 8 months ago by HysenEcho
  0

• Bad webstie connection on README

  #40 opened 9 months ago by LucivorLin
  1

• [0.3.2] 代码补全有多个内容完全相同的选项

  #36 opened 9 months ago by DreamLand7707
  2

• [0.3.2] Linter(vivado) 启用无效 (还是说我用的vivado2023太新了?)

  #32 opened 9 months ago by DuBirdFly
  1

• 仿真时因为文件夹名字存在空格产生错误

  #24 opened 9 months ago by Muione
  1

• 悬停提示对 /**/ 型的注释有误

  #25 opened 9 months ago by DuBirdFly
  2

• Add Questa-Sim into the linter option

  #26 opened 10 months ago by stormkidorg
  1

• WSL环境点击“显示当前文件的FSM图”时会发生扩展远程主机终止的错误

  #20 opened a year ago by Mozes-Y
  0

• 插件一定会生成prj文件夹

  #19 opened a year ago by DuBirdFly
  1

• code to doc

  #21 opened a year ago by Hqf2013
  1

• 语法识别错误

  #22 opened a year ago by Hqf2013
  1