/RISC-V_pipeline_model

MIPT homework. RISC-V pipeline verilog model. Uses verilator for tracing purposes.

Primary LanguageVerilog

RISC-V verilog model

Base on book "Digital Design and Computer Architecture" chapter 7

Requirements

verilator and ELFIO

Optionally gtkwave

Usage

mkdir build && cd build
cmake ..
make
./Vtop <path-to-riscv-executable>

Only rv32i instructions are supported.