2 INPUT/OUTPUT Parallel 8 Tap FIR Filter written in VHDL , compiled, simulated and synthesized using Xilinx Vivado.
One 8 tap FIR filter mathematical expression:
and two 4 tap (for simplicity) parallel FIR filters:
- We wanted the design to be pipelined (1 cycle latency) and the critical path to be as small as possible (Great Clock frequency)
- As few filp flops as possible used.
- When valid_in=0, current state of the system must remain stable: Idea: "gated clock" --> chip enable.
Implementation was done following a "structural" methodology and using behavioral VHDL. More specifically the modules constructed were:
- Input Module 2.Multiplier Module and 3. Adder Module. The idea is shown in the image below (for 4 Tap filter but the same logic is applied for 8 tap).
By compining the above modules, one is able to implement one 1 I/O FIR filter. In order to add pipeline to the filter, extra flip flops must be added as shown in the "lines" and "dots" in the schematics below.
We can construct the 2-Parallel pipelined FIR Filter by compining 2 identical FIR module above. Only difference is , we have to give the correct inputs, so the only module that needs to be changed in the (now common for both Filters) input module.
Input module:
- RTL produced by Vivado
- Behavioral Simulation
- Utilisation
- Critical Path
Note that pipeline produces correct results after 10 Clock Cycles and initial reg values are 0.Also, utilisation and critical path are result of synthesis and not implementation
- Board Used: Zybo (xc7z010clg400-1) , Zynq-7000 product family.
- Xilinx Vivado 2018.2.1
Available only upon request.
Dimitrios Lampros