Pinned Repositories
basics-graphics-music_y
FPGA exercise for beginners
Keras_age_gender
Easy Real time gender age prediction from webcam video with Keras
midi
otus_algo
QSNMP-CA
QT Snmp common agent
wb-ipmi
IPMI driver for MQTT Wirenboard
wb-snmp
SNMP subaget for WirenBoard
yrv-omdazz
yrv-plus
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
yrv-plus-omdaz-16
DmitryZlobec's Repositories
DmitryZlobec/yrv-omdazz
DmitryZlobec/midi
DmitryZlobec/wb-ipmi
IPMI driver for MQTT Wirenboard
DmitryZlobec/Keras_age_gender
Easy Real time gender age prediction from webcam video with Keras
DmitryZlobec/QSNMP-CA
QT Snmp common agent
DmitryZlobec/wb-snmp
SNMP subaget for WirenBoard
DmitryZlobec/yrv-plus
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
DmitryZlobec/yrv-plus-omdaz-16
DmitryZlobec/age-and-gender-classification
Age and Gender Classification using Convolutional Neural Network
DmitryZlobec/basics-graphics-music_y
FPGA exercise for beginners
DmitryZlobec/DigitalDesign
DmitryZlobec/otus_algo
DmitryZlobec/2022-bishkek
DmitryZlobec/74xx-liberty
DmitryZlobec/ahb_lite_sdram
SDRAM controller for MIPSfpga+ system
DmitryZlobec/Altera-Cyclone-IV-board-V3.0
Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board
DmitryZlobec/basics-graphics-music
DmitryZlobec/FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
DmitryZlobec/hdmi
DmitryZlobec/Karnix_ASB-254
Karnaugh Interactive Extendable ASIC Simulation Board AKA Karnix ASB-254
DmitryZlobec/kicad-iso-library
My kicad library (pcb symbols needs extended layer support)
DmitryZlobec/ostep-code
Code from various chapters in OSTEP (http://www.ostep.org)
DmitryZlobec/ostep-homework
DmitryZlobec/ostep-projects
Projects for an undergraduate OS course
DmitryZlobec/problems_012_019
DmitryZlobec/QSNMP-BIN
DmitryZlobec/qt-solutions
DmitryZlobec/risc-666
RISC-V user-mode emulator that runs DooM
DmitryZlobec/uart
A simple implementation of a UART modem in Verilog.
DmitryZlobec/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation