Pinned Repositories
ArtyS7
Where Arty S7 projects are kept. MIT License unless file headers state otherwise.
ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
BenchPower1
Schematics, Firmware & Simulations for a simple linear Bench Power Supply
miniSpartan3
Projects for the miniSpartan3 board from Scarab Hardware
misc
General things not associated with a particular project.
riscv-compliance
RPU
Basic RISC-V CPU implementation in VHDL.
TeensyZ80
Code and related parts of the TeensyZ80 project.
TPU
TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
UART
Simple UART implementation in VHDL
Domipheus's Repositories
Domipheus/RPU
Basic RISC-V CPU implementation in VHDL.
Domipheus/TPU
TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
Domipheus/ArtyS7-RPU-SoC
Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
Domipheus/TeensyZ80
Code and related parts of the TeensyZ80 project.
Domipheus/ArtyS7
Where Arty S7 projects are kept. MIT License unless file headers state otherwise.
Domipheus/UART
Simple UART implementation in VHDL
Domipheus/misc
General things not associated with a particular project.
Domipheus/BenchPower1
Schematics, Firmware & Simulations for a simple linear Bench Power Supply
Domipheus/miniSpartan3
Projects for the miniSpartan3 board from Scarab Hardware
Domipheus/riscv-compliance
Domipheus/SDDatalogger1
A 4-channel analog SD Card datalogger with RTC