[export-dot] Incorrect width for constant value in legacy modes

[lucas-rami]

The export-dot tool behaves incorrectly in legacy modes when printing nodes corresponding to constant operations in the DOT. The value of the value node annotation does not respect the bitwidth of the constant under consideration. This makes the legacy dot2vhdl tool behave incorrectly down the line and create an incorrect bitwidth assignment in the generated VHDL. For example, running the following benchmark using the Dynamatic frontend fails during simulation.

int share_test(in_int_t a[1000], in_int_t b[1000]) {
  int i;
  int tmp = 0;
  for (i = 0; i < 1000; i++)
    tmp += a[i] * b[999 - i] * 787879;
  for (i = 0; i < 1000; i++)
    tmp += a[999 - i] * b[i];
  return tmp;
}

Modelsim produces the following error

# ** Error (suppressible): [...]/share_test.vhd(1926): (vcom-1272) Length of expected is 21; length of actual is 32.

for the constant holding the value 787879, which is represented in the DOT as

"constant4" [in="in1:21", out="out1:21", value="0x000c05a7" /* more annotations */]

[lucas-rami]

Note that while the part of the code handling this was cleaned up and somewhat fixed it does not fix the Modelsim failure, which is actually due to dot2vhdl producing an incorrect VHDL or to the HLS verifier failing to parse it correctly for this specific benchmark (the same problem occurs for this benchmark with legacy Dynamatic).

The constant width-related error shown above is suppressible and also appears with legacy-generated DOTs.