EPFL-LAP/dynamatic

Issues

• [Backend] Chisel LSQ generator fails on LSQs with 0 load ports

  #111 opened 4 months ago by AyaElAkhras
  7

• [handshake] failed to legalize operation 'arith.*'

  #115 opened 3 months ago by Jiahui17
  1

• [LSQ] Cannot determine control signal for BB X

  #121 opened 3 months ago by Jiahui17
  0

• [Backend] Incompatible lsq port naming in top-level module

  #116 opened 3 months ago by Jiahui17
  2

• [Backend] Incorrect/incomplete MC port naming and mem_to_bram in module instantiation

  #117 opened 3 months ago by Jiahui17
  2

• [Backend] Incorrect port naming in the testbench module instantiation

  #114 opened 3 months ago by Jiahui17
  3

• [scf] memory out-of-bound error

  #119 opened 3 months ago by Jiahui17
  1

• [Minimize LSQ Usage] Optimization fails with fast token delivery circuits

  #110 opened 4 months ago by AyaElAkhras
  1

• [Backend] Simulation hang in a circuit without loop

  #118 opened 3 months ago by Jiahui17
  1

• [Backedge] Assertion violation in Backedge.cpp

  #113 opened 3 months ago by Jiahui17
  0

• Circuit/Memory interface redesign

  #88 opened 5 months ago by lucas-rami
  0

• Buffering redesign

  #87 opened 4 months ago by lucas-rami
  0

• "llvm-projects" submodule error

  #109 opened 4 months ago by ylshaa
  0

• Type system redesign

  #86 opened 5 months ago by lucas-rami
  0

• [CfToHandshake] External function bug in CfToHandshake conversion

  #108 opened 4 months ago by Carmine50
  0

• [HandshakeSimulator] Design proposal and tracking issue

  #94 opened 5 months ago by lucas-rami
  2

• [Handshake] Improve assembly format of `BundleOp` and `UnbundleOp`

  #99 opened 4 months ago by lucas-rami
  0

• [Handshake] Add Handshake versions of missing `arith`/`math` operations

  #102 opened 5 months ago by lucas-rami
  0

• Improve project documentation

  #89 opened 5 months ago by lucas-rami
  0

• Compile error by switching order of two for loops,failing to generate LSQs

  #81 opened 6 months ago by jirheee
  2

• [integration-test] expecting channel<f32> but get channel<i32>

  #80 opened 6 months ago by Jiahui17
  2

• Wrong result used in integration tests

  #79 opened 6 months ago by chatpion
  2

• Unable to complete build. -- Build Failed --

  #74 opened 8 months ago by Technorico
  4

• [HLSVerifier] Integrate HLS verifier from legacy Dynamatic into Dynamatic++

  #21 opened 10 months ago by lucas-rami
  1

• [Buffers] Tracking issue for smart buffer placement pass(es)

  #16 opened a year ago by lucas-rami
  0

• [LSQ] Tracking issue for LSQ support

  #15 opened a year ago by lucas-rami
  1

• [LSQ] FPT'19 flow analysis to minimize LSQ usage

  #56 opened a year ago by lucas-rami
  0

• [Back Annotation] Back Annotation Ignoring Buffer Constraints

  #59 opened a year ago by kb29x37
  1

• [export-dot] Incorrect width for constant value in legacy modes

  #54 opened a year ago by lucas-rami
  1

• [handshake-sim] Formalized dataflow state management

  #44 opened a year ago by lucas-rami
  0

• [LSQ] Formalize and modularize LSQ placement logic

  #52 opened a year ago by lucas-rami
  0

• [LSQ] Support for annotations to drive memory interface placement

  #50 opened a year ago by lucas-rami
  0

• [Handshake] Overall `MemoryControllerOp`'s definition

  #41 opened a year ago by lucas-rami
  1

• [Handshake] Improve `MemoryControllerOp` operation format

  #49 opened a year ago by lucas-rami
  0

• Support for generic back-annotations

  #47 opened a year ago by lucas-rami
  0

• Add support infrastructure for associating attributes to operands

  #46 opened a year ago by lucas-rami
  0

• Assign a unique name to each IR operation

  #45 opened a year ago by lucas-rami
  0

• [Buffers] Support for channel-specific combinational delays

  #43 opened a year ago by lucas-rami
  0

• Preserve original C function argument names in MLIR

  #22 opened a year ago by lucas-rami
  1

• [OptimizeBitwidths] Make the `scf::ForOp` lowering create unsigned comparisons when possible

  #28 opened a year ago by lucas-rami
  0

• [OptimizeBitwidths] Better heuristic for promoting signed comparisons to unsigned

  #26 opened a year ago by lucas-rami
  1

• [Buffers] No throughput constraints for least frequently executed `arith::SelectOp` input

  #36 opened a year ago by lucas-rami
  0

• [export-dot] Use latencies from smart buffer placement pass in DOTs

  #18 opened a year ago by lucas-rami
  0

• [export-vhdl] Missing VHDL entities for remainder operations

  #33 opened a year ago by lucas-rami
  0

• [OptimizeBitwidths] Optimize away the sign bit when possible

  #30 opened a year ago by lucas-rami
  0

• [RotateForLoops] Add unit tests to loop rotation pass

  #27 opened a year ago by lucas-rami
  0

• [export-dot] Make bitwidth optimized circuits compatible with legacy Dynamatic

  #17 opened a year ago by lucas-rami
  0

• [OptimizeBitwidths] Handle optimization of data cycles

  #14 opened a year ago by lucas-rami
  0

• Add GitHub CI/CD flow to run on each PR/commit

  #19 opened a year ago by lucas-rami
  0