EasonIp

Pinned Repositories

CodeHub
Eason 2017-2020
0 2 00
CodeHub2917-2019
Eason 2017-2020
0 2 00
DE2_BookCodeYouJing
DE2 book code_youjing;
Language:Verilog0 1 00
DE2_YT_Project
Language:C0 1 01
DSP_YT_Project
Language:C0 1 00
Filter_FPGAwithMATLAB
Filter_FPGAwithMATLAB
Language:Verilog7 2 01
FPGA_demo-ex1
《FPGA设计实战演练（逻辑篇）》 code
Language:VHDL0 1 00
Heijin
Language:Verilog0 1 00
Lichuying_code
Lichuying_code
Language:VHDL0 1 00
Vivado_Project
AX7020_board
Language:VHDL1 1 01

EasonIp's Repositories

EasonIp/Filter_FPGAwithMATLAB
Filter_FPGAwithMATLAB
Language:Verilog7 2 01
EasonIp/Vivado_Project
AX7020_board
Language:VHDL1 1 01
EasonIp/CodeHub
Eason 2017-2020
0 2 00
EasonIp/CodeHub2917-2019
Eason 2017-2020
0 2 00
EasonIp/DE2_BookCodeYouJing
DE2 book code_youjing;
Language:Verilog0 1 00
EasonIp/DE2_YT_Project
Language:C0 1 01
EasonIp/DSP_YT_Project
Language:C0 1 00
EasonIp/FPGA_demo-ex1
《FPGA设计实战演练（逻辑篇）》 code
Language:VHDL0 1 00
EasonIp/Heijin
Language:Verilog0 1 00
EasonIp/Lichuying_code
Lichuying_code
Language:VHDL0 1 00
EasonIp/modelsim_pjt
Language:Verilog1 0
EasonIp/pyvivado
Python tools for Vivado Projects
Language:Python1 0
EasonIp/SystemVerilogAssertions
Examples and reference for System Verilog Assertions
Language:SystemVerilog1 0
EasonIp/SystemVerilogReference
training labs and examples
Language:SystemVerilog1 0
EasonIp/UVMReference
Reference examples and short projects using UVM Methodology
Language:SystemVerilog1 0
EasonIp/Vivado-Prj
EasonIp/ZhiXinClass1
ZhiXinClass1;
Language:Verilog
EasonIp/ZhiXinClass2
ZhiXinClass2
Language:C1 0