/DSD_final_project

2020 Spring DSD Final Project, NTUEE

Primary LanguageVerilog

DSD_final_project

2020 Spring Digital System Design Final Project, NTUEE

Intro

Baseline

  • Pipelined MIPS
  • Haszard handling

Extension

  • Branch prediction
  • L2 cache
  • Multiply & divide

Detailed introduction in DSD_Final_Project_MIPS_G3/report.pdf.

Usage

ncverilog -f files_[condition].f +define+[condition] +access+r