In this repository you will find several VHDL projects along with simulation and constraint files to test their functionality by simulating them or on a Basys 3 FPGA Board.
Implementation of an encoder + Simulation file
Implementation of a system that receives as input 16 2-bit numbers and returns the lowest number.
It is designed in a structural way, the lowest_num entity consists of 15 cells that are implemented using a Comparator and a Multiplexer. Simulation files are included.
Implementation of a parity checker for an n-bit number using xor operator.
Lab 1 consists of an introduction to VHDL and the GUI of Vivado.
- 1a: Implementation of a 4-bit adder + Simulation and constraints file
- 1b: Implementation of a register with parallel input and parallel output + Simulation and constraints file
- 1c: Implementation of a Mod-16 counter in a structural way using the modules adder (1a) and register (1b) + Simulation and constraints files
Lab 2 consists on the implementation of an 8 bit digital combinational lock as a Finite State Machine (FSM).
The project is designed in a structural way using a Debouncer, Decimal to 7-segment converter (for 7-segment display), Register, Comparator and FSM(lock).
- 2a: First implementation (just one button for setting passwd and guessing)
- 2b: Second implementation (two buttons, one for setting passwd and other for guessing)
The lock is initially open (LED on), when the push button is pressed, the key is internally stored in a register and the lock is closed (LED off). After that, the user has 3 attempts (pressing the push button) to open the lock. The values of the register and the new imput are compared and the remaining attemps are displayed in the 7-segment display.
This consists on modifying some aspects of 2a. Now we use two buttons, one to enter the initial password and other one to guess it. When the FSM is in state Three, Two or One, if the user pushes the button to enter a new initial password, it will be saved and the FSM goes back to state Three.
Lab 3 is about iterative networks.
- Network 1 consists on implementing an interative networks in 1-D in order to find the maximum among several numbers.
- Networks 2 is the same as Network 1 but it is implemented in 2D (tree-shaped)
Both networks are defined generically for any quantity of numbers (at least powers of 2).
This consists on modifying Network 2 of 3a to add some registers.
Lab 4 is about a sequencial divider. It consists on coding an ASM system that implements an algorithm for dividing two numbers.
The final lab is about a microprocessor using a MIPS multicycle implementation.
The goal is to implement some instructions (move with register, move with immediate and unconditional jump)
- R-Type instructions: arithmetic-logical
- add rd, rs, rt : [ rd <- rs + rt ; PC <- PC + 4 ]
- sub rd, rs, rt : [ rd <- rs - rt ; PC <- PC + 4 ]
- and rd, rs, rt : [ rd <- rs and rt ; PC <- PC + 4 ]
- or rd, rs, rt : [ rd <- rs or rt ; PC <- PC + 4 ]
- nor rd, rs, rt : [ rd <- rs nor rt ; PC <- PC + 4 ]
- xor rd, rs, rt : [ rd <- rs xor rt ; PC <- PC + 4 ]
- I-Type instructions: with memory, conditional branch, with immediate
- lw rt, immed(rs) : [ rt <- Mem(rs + SignExt(immed)) ; PC <- PC + 4 ]
- sw rt, immed(rs) : [ Mem(rs + SignExt(immed)) <- rt ; PC <- PC + 4 ]
- beq rs, rt, immed : if (rs == rt) then { PC <- PC + 4 + 4*SignExt(immed) } else { PC <- PC + 4 }
- mv rt, #immed : [ rt <- SignExt(immed) ; PC <- PC + 4 ]
- mv rt, rs : [ rt <- rs ; PC <- PC + 4 ]
- J-Type instructions: jump (unconditional branches)
- j instr : [ PC <- 0000 & instr & 00 ]