Pinned Repositories
AAML-f21
Accelerator Architectures for Machine Learning homework NYCU 2021
bigData
大数据比赛项目库
chisel-tutorial
chisel tutorial exercises and answers
CornellCSWiki
Student-run wiki for students interested in computer science at Cornell University
esp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
Final-project-of-cpp
a game of majictower
git-blog-demo
github-slideshow
A robot powered training repository :robot:
gitqwerty777.github.io
Used for a site
Learn-CS61A-2020
Elena32061's Repositories
Elena32061/AAML-f21
Accelerator Architectures for Machine Learning homework NYCU 2021
Elena32061/bigData
大数据比赛项目库
Elena32061/chisel-tutorial
chisel tutorial exercises and answers
Elena32061/CornellCSWiki
Student-run wiki for students interested in computer science at Cornell University
Elena32061/esp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
Elena32061/Final-project-of-cpp
a game of majictower
Elena32061/git-blog-demo
Elena32061/github-slideshow
A robot powered training repository :robot:
Elena32061/gitqwerty777.github.io
Used for a site
Elena32061/Learn-CS61A-2020
Elena32061/matrixsum
fall13 lab, UCB.
Elena32061/my_chisel_example
my hisel_example
Elena32061/Python-100-Days
Python - 100天从新手到大师
Elena32061/Quest
[ICML 2024] Quest: Query-Aware Sparsity for Efficient Long-Context LLM Inference
Elena32061/rainbowpoem_demo
This is test repo
Elena32061/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Elena32061/scale-sim-v2
Repository to host and maintain scale-sim-v2 code
Elena32061/sp21-aes-rocc-accel
AES RoCC Accelerator
Elena32061/streaming-llm
[ICLR 2024] Efficient Streaming Language Models with Attention Sinks
Elena32061/Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
Elena32061/Test
Elena32061/TNoC-Topology-Reconfigurable-NoC-Generator
TNoC
Elena32061/tptpu-sim
A Toy-Purpose TPU Simulator
Elena32061/Useful-Academic-Links
This repo has some usefull links to websites for topics, please fork add and generate a pull-request to join the party
Elena32061/Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code
A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. There are many other use of FIFO also. FIFO uses a dual port memory and there will be two pointers to point read and write addresses. Here is a generalized block diagram of FIFO.