/Synthesizable-ALU-in-VHDL

Primary LanguageC

ALU in VHDL

This is ISE(Xilinx) project which I implement a simple alu in vhdl.

this alu can handle below operations:

1- sum

2- sub

3- multiplication

4- division

5- power

6- sqrt

all of this operations are in ALU_OP package (ALU_OP.vhd) and they are imported in main file (ALU.vhd)